S. Das C. Karfa and S. Biswas, “Formal modeling of network-on-chip using cfsm and its application in detecting deadlock” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 4, pp. 1016-1029, April 2020, doi: 10.1109/TVLSI.2019.2959618, Link
S. Das and C. Karfa, “Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC” in IEEE Embedded Systems Letters, vol. 14, no. 2, pp. 67-70, June 2022, doi: 10.1109/LES.2021.3113355, Link
S. Das C. Karfa and S. Biswas, “Accelerating NoC Verification Using a Complete Model and Active Window” in IEEE Access, vol. 10, pp. 88985-88999, 2022, doi: 10.1109/ACCESS.2022.3199671, Link
Journals
S. Das, Et al., “RTL Simulation Acceleration with Machine Learning Models,” 2024 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024, pp. 1-7, Link
S. Das and C. Karfa, “Formal Modeling and Verification of Starvation-Freedom in NoCs” in Embedded Computing and System Design - 10th International Symposium, ISED 2021, Gandhinagar, Link
S. Das and C. Karfa, “Deadlock Avoidance in Torus NoC Applying Controlled Move via Wraparound Channels” in Embedded Computing and System Design - 10th International Symposium, ISED 2021, Gandhinagar, Link
S. Das, C. Karfa and S. Biswas, “xmas Based Accurate Modeling and Progress Verification of NoCs” in VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, Link
S. Das, S. Das and H. K. Kapoor, “Tag Only Storage for Capacity Optimised Last Level Cache in Chip Multiprocessors,” 20th International Symposium on VLSI Design and Test, Link
S. Das, D. Gopalani, “Big Data Analysis Issues And Evolution Of Hadoop,” IJPRET, 2014; Volume 2 (8): 152-161, Link